IPROVF1 · PCIe Gen5 ×16 inference accelerator
MediaChipset accelerators put 48 TB/s of 3D-stacked memory beneath 1000 TFLOPS of FP8 compute on a standard PCIe card. Token generation becomes compute-bound at a batch of about 21 instead of several hundred, so the interactive, low-batch traffic that real applications generate runs at full efficiency.
Pre-silicon specifications are design targets.
The inference bottleneck
Training GPUs ship roughly 400 FLOP of compute per byte of memory bandwidth, a ratio tuned for gradient computation. Token generation is different: every new token streams the entire model from memory.
To keep their arithmetic units fed, serving stacks batch hundreds of requests together, and users pay for it in latency. IPROVF1 inverts that balance with ten times the memory bandwidth of a 4.8 TB/s part, so a single conversation, agent step or robot control loop gets served at memory speed.
Where a single card trails a flagship GPU, on peak dense compute (1000 vs ≈1980 TFLOPS FP8) and capacity (64 vs 141 GB), two cards linked as IPROVF2 close the gap while doubling the bandwidth lead again to 96 TB/s.
How the architecture gets thereTB/s, higher is better
tokens per second, higher is better
concurrent requests, lower is better
H200 values are NVIDIA-published dense figures for H200 SXM. IPROVF1 values are design targets; decode throughput is the bandwidth-bound ceiling (bandwidth ÷ model bytes).
Products
Start with a card that drops into any PCIe Gen5 server, or deploy a MediaChipset server integrated and validated with the serving stack.
A full-height PCIe Gen5 ×16 accelerator for 3B–20B models at interactive latency, with up to ≈50B parameters resident in FP8.
Four or eight IPROVF1 cards in a validated system, shipped with the driver, runtime and vLLM serving stack installed. Serve many mid-size models side by side, or pair cards for 50B–100B models.
Why IPROVF1
A 13B FP8 model sustains ≈3,700 tok/s at batch 1, against ≈370 tok/s on a 4.8 TB/s part.
1000 TFLOPS FP8 and 500 TFLOPS BF16 dense in a card for any PCIe Gen5 server. No bespoke chassis or switch fabric.
3B–20B models fit entirely in FP8 with tens of gigabytes left for KV cache. No sharding, no collectives in the critical path.
A native attention engine keeps the score tile on die, so long-context serving is limited by memory capacity, not on-chip storage.
One dual-mode PE issues two FP8-E4M3 MACs or one BF16 MAC per cycle. Official FP8-dynamic checkpoints load directly.
The MediaChipset SDK plugs into PyTorch, Hugging Face and vLLM today, validated model by model across LLM, vision-language and VLA workloads.
Validated software
The MediaChipset SDK is validated against the reference GPU implementation on text LLMs, vision-language and vision-language-action models, in both BF16 and FP8 W8A8. Bring-up on silicon is a port, not a rewrite.
Measured on the IPROVF-Sim validation stack.
The IPROVF family
Every configuration runs the same compiler, runtime and model formats.
| Configuration | FP8 compute | Memory | Target models |
|---|---|---|---|
| IPROVF1 | 1000 TFLOPS | 64 GB · 48 TB/s | 3B–20B at interactive latency; up to ≈50B resident |
| IPROVF2 (2×) | 2000 TFLOPS | 128 GB · 96 TB/s | 50B–100B |
| IPROVF4 (4×) | 4 PFLOPS | 256 GB | up to ≈200B |
| IPROVF48 (48×) | 48 PFLOPS | 3 TB | trillion-parameter class |
IPROVF1 and IPROVF2 are the standard packages; IPROVF4 and IPROVF48 are super-chipset configurations of the same architecture. Two devices form IPROVF2 over a 1.0 TB/s die-to-die link.
Customer data room
The full IPROVF1 datasheet and engineering documentation are shared with customers through a secure data room. Every download is logged and stamped to the recipient.
Tell us who you are and what you're evaluating. Use your business email.
We confirm a mutual NDA is in place, or send you one to sign, then approve your account.
Set your password from the single-use invitation and download documents for the term of your NDA.